(1) Field of the Invention
The invention relates to a method of controlling the critical dimension width of polysilicon, and more particularly, to a method of controlling the critical dimension width of polysilicon by using a disposable hard mask to eliminate critical dimension variation in the manufacture of integrated circuits.
(2) Description of the Prior Art
Referring to FIG. 1, there is shown a portion of a partially completed integrated circuit in which there is a silicon substrate 10. Field oxide regions 12 are formed in and on the silicon substrate resulting in a uneven topography of the top surface of the substrate. A gate oxide layer 14 is grown on the surface of the substrate and the field oxide regions. A layer of polysilicon 16 is deposited over the gate oxide layer. A layer of photoresist 18 covers the surface of the substrate and planarizes the substrate. The differing photoresist depths A and B will make an imperfect image and resulting mask, causing critical dimension variation. Due to the standing-wave phenomenon, different resist thicknesses result in different resist dimensions; this is known as the swing-effect. Also, the polysilicon on the sloped edge of the field oxide region reflects light 20 during photolithographic exposure, resulting in necking.
FIG. 2 shows the integrated circuit chip after photolithography and etching with completed polysilicon lines 16A, 16B, and 16C. FIG. 3 shows a top view of FIG. 2, including field oxide regions 12, active areas 22, and polysilicon lines 16A, 16B, and 16C. The mask used has the same dimensions for polysilicon lines 16A and 16B, but different dimensions are printed on the photoresist mask because of the different photoresist thicknesses on the topography. Resulting polysilicon line 16A has a different dimension than polysilicon line 16B because of the photoresist thickness difference (A and B in FIG. 1) due to different elevations. This figure also illustrates the necking problem 24 in polysilicon line 16C, especially for areas having a large change in topography such as the field oxide to active areas. This necking problem could result in early breakdown of the integrated circuit via the neck, 24.
U.S. Pat. No. 5,324,689 to Yoo uses spin-on-glass to planarize the photoresist underlayer to control critical dimension width. U.S. Pat. No. 5,354,713 to Kim et al uses spin-on-glass and etchback to flatten the insulating layer between metal lines. U.S. Pat. No. 5,350,486 to Huang uses spin-on-glass in a planarization process.